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LTC4274
11
4274fd
 I
2
C TIMING DIAGRAMS
Figure 6. Writing to a Register
Figure 7. Reading from a Register
SCL
SDA
4274 F06
0
0
1
AD3  AD2  AD1  AD0
A7   A6   A5   A4   A3   A2    A1   A0
R/W  ACK
D7   D6   D5   D4   D3   D2    D1   D0
ACK
ACK
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
STOP BY
MASTER
SCL
SDA
0
0
1
AD3  AD2  AD1  AD0
A7   A6   A5   A4   A3   A2    A1   A0
R/W  ACK
ACK
0
0
1
AD3  AD2  AD1  AD0
D7   D6   D5   D4   D3   D2    D1   D0
R/W  ACK
ACK
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
4274 F07
STOP BY
MASTER
REPEATED
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
Figure 8. Reading the Interrupt Register (Short Form)
Figure 9. Reading from Alert Response Address
SCL
SDA
4274 F08
0
1
0   AD3  AD2  AD1  AD0
D7   D6   D5   D4   D3   D2    D1   D0
R/W  ACK
ACK
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
STOP BY
MASTER
SCL
SDA
4274 F09
0
0
1
1
0
AD3
0
0
0
0
1
AD2  AD1 AD0
R/W  ACK
ACK
1
START BY
MASTER
ACK BY
SLAVE
 NO ACK BY
MASTER
FRAME 1
ALERT RESPONSE ADDRESS BYTE
FRAME 2
SERIAL BUS ADDRESS BYTE
STOP BY
MASTER
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